Confirmed open46 days ago
First seen2 months ago
Remoet re-checks every listing roughly once a day.Senior or Staff Design Verification Engineer role using SystemVerilog and UVM in a hybrid office environment.
Summary, tech stack, seniority and salary here are extracted or inferred by Remoet, not the employer's own words.Salary
$160,000 - $190,000/yearTech stack
SystemVerilogUVMVerilogSVAPythonPerlUNIXLinuxXceliumVCS
Benefits
Stock option grantHealth insuranceDental insuranceVision insurance401(k)
Confirmed open46 days ago
First seen2 months ago
Remoet re-checks every listing roughly once a day.