Senior or Staff Design Verification Engineer

Vancouver, WA; Chandler, AZ

Hybridsenior

Confirmed open13 minutes ago

First seentoday

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Senior or Staff Design Verification Engineer role using SystemVerilog and UVM in a hybrid office environment.

Summary, tech stack, seniority and salary here are extracted or inferred by Remoet, not the employer's own words.

Salary

$160,000 - $190,000/year

SystemVerilogUVMVerilogSVAPythonPerlUNIXLinuxXceliumVCS

Stock option grantHealth insuranceDental insuranceVision insurance401(k)

Confirmed open13 minutes ago

First seentoday

Remoet re-checks every listing roughly once a day.