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Powerlattice

Power delivery chiplet company designing analog/digital ICs and architectures for next-gen compute power.

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Open roles at Powerlattice

7 roles
Senior Digital Design Engineer
Chandler, AZ / Hybrid / $150,000 - $200,000/year
Validation Engineering Lead
Chandler, AZ / On-site
Sr. Field Applications Engineer - Power Delivery
San Jose, CA / Hybrid / $150,000 - $225,000/year
Senior or Staff Hardware Design Engineer
Chandler, AZ / On-site / $150,000 - $200,000/year
Senior/Staff Analog IC Design Engineer
Chandler, AZ / Hybrid / $150,000 - $200,000/year
Power Delivery Solution Architect
Chandler, AZ / Hybrid / $180,000 - $250,000/year
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About

PowerLattice builds a power delivery chiplet that sits inside the processor package, moving voltage regulation next to AI accelerators, GPUs, and data-center processors instead of inches away on the board.

Founded in 2023 by Peng Zou, Gang Ren, and Sujith Dermal, all electrical engineers out of Qualcomm, NUVIA, and Intel. Came out of stealth in November 2025 with a $25M Series A led by Playground Global and Celesta Capital, bringing total funding to $31M. Pat Gelsinger, former Intel CEO and now a GP at Playground, is among the investors.

First chiplets are in production at TSMC, with broader customer testing planned for H1 2026. Offices in Vancouver, WA and Chandler, AZ.