PCB Layout Engineer, Robotics

San Francisco
Hybridmid
Confirmed openyesterday
First seenyesterday
Remoet re-checks every listing roughly once a day.
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Mid-level PCB Layout Engineer role in San Francisco using Cadence Allegro, hybrid work, $318k-$485k per year.

Summary, tech stack, seniority and salary here are extracted or inferred by Remoet, not the employer's own words.

Salary

$318,000 - $485,000/year

Tech stack

Cadence Allegro PCB DesignerCadence Constraint ManagerCadence SigrityAnsys SIwaveCadence SKILL

Benefits

Health insuranceRetirement plansEqual opportunity employer
Confirmed openyesterday
First seenyesterday
Remoet re-checks every listing roughly once a day.
Apply on OpenAIYou will apply on OpenAI's own site.Star OpenAI to hear about new roles →