FPGA Verification Engineer, Air Dominance and Strike

Costa Mesa

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Mid-level FPGA Verification Engineer role in Costa Mesa using UVM and SystemVerilog, paying $146k-$194k annually.

Summary, tech stack, seniority and salary here are extracted or inferred by Remoet, not the employer's own words.

Salary

$146,000 - $194,000/year

SystemVerilogUVMSVAAMDXilinxQuestaVCSXceliumVivadoGitLinuxSVUnitPythonTclMakefileEthernetPCIeJESD204CMIL-STD-1553SPI

Comprehensive benefits packageEquity grants

Confirmed open1 hour ago

First seentoday

Remoet re-checks every listing roughly once a day.