FPGA Verification Engineer, Air Vehicles

Costa Mesa

On-sitemid

Confirmed open29 days ago

First seen4 weeks ago

Remoet re-checks every listing roughly once a day.

Mid-level FPGA Verification Engineer role in Costa Mesa using UVM and SystemVerilog, paying $123k-$171k annually.

Summary, tech stack, seniority and salary here are extracted or inferred by Remoet, not the employer's own words.

Salary

$123,000 - $171,000/year

SystemVerilogUVMSVAPythonTclMakefileGitLinuxAMDXilinxEthernetPCIeJESD204CMIL-STD-1553SPIARM

Comprehensive benefits packageEquity grants

Confirmed open29 days ago

First seen4 weeks ago

Remoet re-checks every listing roughly once a day.